An important problem in designing and fabricating very large scale integrated circuits is the inaccessibility of many of the internal nodes and so, internal signals. This makes it difficult to discern engineering problems, debug the design, and adequately to test the circuit before it is incorporated into its system environment.
Various solutions have been proposed to solve this problem. These originally involved testing the circuit with complex input test patterns that attempted to exercise all the internal circuits and propagate the state of internal signals to the output pins of the integrated circuit chip where they could be measured. As integrated circuits become more complex, the input patterns, to do a satisfactory job, increase in length sharply; and it soon becomes economically impractical to do a thorough job of testing.
Other approaches have involved the inclusion of special circuitry which when activated makes the condition of selected internal nodes of particular interest directly available at specified pins of the chip. However, with increased circuit complexity, the number of internal nodes of particular interest grows to a point where this approach is inadequate.
One promising approach that has been developed for sequential, large-scale integrated circuits and has a number of variations is generally known as scan design. See, for example, a paper entitled "Design for Testability of the IBM System/38" by L. A. Stolte and N. C. Berglund presented at the 1979 IEEE Test Conference, Cherry Hill, N.J. which is in the Proceedings of this Conference, pp. 29-36. Scan design makes a digital circuit testable by providing a scan mode in which all the storage elements in the circuit, except the memory arrays, have their data inputs and outputs effectively disconnected from the combinational part of the circuit and reconnected internally to form one or more shift registers. This is accomplished typically by adding multiplexing circuits at the data inputs of the storage elements which permit switching functionally the interconnections and so the operating mode of the circuit between the normal operation and the scan mode operation. Hitherto, the switching between the two modes has involved the application of a separate scan mode switching signal to the multiplexer associated with each storage element to control its operating mode. The need to route this mode switching signal to the various multiplexers can pose problems in very large scale integrated circuits where it is important to conserve space. Accordingly, it would be advantageous to avoid the routing of this switching signal between the storage elements and so to save the space such routing requires.